The present invention relates to integrated circuit devices, and more particularly, to integrated circuit memory devices.
Static random access memories (SRAMs) are typically high speed memory devices, with relatively low power consumption, which generally do not need to refresh data. SRAMs may be effectively employed in mobile equipment, such as cellular phones. Generally, SRAM memory cells include two inverters that form a flip-flop circuit to which two pass transistors are coupled. Conventional SRAM cells may be classified into load SRAM and CMOS SRAM. In load SRAM, pull down transistors and a load coupled to the pull down transistors are generally included in inverters, which, in turn, form a flip-flop circuit. A resistor or a thin film transistor may be used as the load. In CMOS SRAM, pull up transistors and pull down transistors, that is, CMOS transistors including PMOS and NMOS transistors, are generally included in inverters, which, in turn, form a flip-flop circuit. The CMOS structure, in which SRAM cells are configured using a CMOS process, may be useful because CMOS SRAM devices generally have superior electrical characteristics in comparison to load SRAM.
Problems may arise when configuring SRAM cells using a CMOS process. For example, it may be difficult to scale down the size of SRAM cells. When configuring SRAM cells in a CMOS process, six transistors may be integrated into a single SRAM cell, and NMOS and PMOS transistors coexist in the single SRAM cell. Therefore, a relatively large space may be required for the SRAM cell.
In addition, a complicated well structure may be needed for separating the NMOS transistors from the PMOS transistors, which may increase the size of the SRAM cell. For example, an N-well for a PMOS transistor would typically be formed within a P-well for an NMOS transistor. The N-well may be formed in a bulk substrate and surround at least the PMOS transistor, which may create a large gap between the NMOS and PMOS transistors. In this regard, there have been numerous studies and attempts to come up with ways to limit an increase in the overall size of SRAM cells caused by such a complicated well structure when configuring SRAM cells for a CMOS process.
Another possible problem is latch-up, which is a problem related to the coexistence of NMOS and PMOS transistors in an SRAM cell configured in a CMOS process. Furthermore, as a gate is scaled down, a soft error rate (SER), which indicates reliability, an important characteristic of SRAMs, may increase.